Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, more particularly to a method of fabricating a semiconductor device for preventing rising-up of siliside.
A high integration of semiconductor integrated circuits such as LSI has developed micronizing of devices. For example, impurity diffusion layers in source and drain regions are formed to be shallow and areas of them are made small. Moreover, a width of wirings connecting the devices are also narrowed. For this reason, electric resistances of the diffusion layers and the wirings are increased, so that a high speed operation of the devices is obstructed. From such circumstances, in the recent semiconductor devices, the attempt is made to form the surface of the impurity diffusion layer by using high melting point metal silicides, particularly by titanium silicide, whereby a high speed operation of the devices can be achieved by an decrease in the resistance of the impurity diffusion layer.
For the formation of the titanium silicide layer, U.S. Pat. No. 4,855,798 discloses the formation of the titanium silcide layer using a self-alignment manner. The method to form the titanium silicide layer in the self-alignment manner will be described with reference to FIGS. 3(a) to 3(g).
As shown in FIG. 3(a), the field oxide film 2, the gate oxide film 3, the gate electrode 4 and the side wall film 5 are formed on the semiconductor substrate 1. The exposed portions 6 of the semiconductor substrate 1 act as a diffusion layer region after impurity ions are injected thereto.
Next, a protection oxide film 7 for the ion injection is formed on the entire surface of the resultant structure using a CVD method, for example, and thereafter impurity ions 8 are injected, thereby forming the diffusion layer 9 (FIG. 3(b)). Subsequently, a thermal treatment at a temperature of not less than 900.degree. C. is performed to activate the diffusion layer 9. That is, the activated diffusion layer 14 is formed.
Thereafter, the protection oxide film 7 is removed, and further a natural oxide film is removed prior to a Ti sputtering (FIG. 3(c)).
Next, as shown in FIG. 3(d), the titanium film 11 is grown on the entire surface of the resultant structure by a sputtering method, for example. The titanium silicide film 11 is subjected to a thermal treatment under the conditions that a temperature is not more than 700.degree. C. in an inert gas atmosphere, for example, a nitrogen atmosphere. Thus, the titanium silicide layer 12 of C49 phase is formed of high resistance TiSi.sub.2 (a first sinter). At this time, the titanium silicide layer 12 only on the gate electrode 4 and the activated diffusion layer 14 in a self-aligned manner FIG. 3(e).
Subsequently, the non-reacted titanium film 11 on the field oxide film 2 and the side wall film 5 is removed (FIG. 3(f)). Furthermore, a thermal treatment at a temperature of not less than 800.degree. C. is performed. As a result of the thermal treatment, the titanium silicide film of C54 phase formed of low resistance TiSi.sub.2 as shown in FIG. 3(g) is formed (a second sinter).
However, when the titanium silicide films are formed by the foregoing method, the development of micronizing of the devices has created the problems of an electrical short-circuit between the gate electrode and the diffusion layers acting as the source/drain regions and between the diffusion layers adjacent to each other. The electrical short-circuits inherently originate from rising-up of the titanium silicide onto the region where the titanium silicide is not formed, that is, onto the side wall film for separating the gate electrode and the diffusion layers and onto the field oxide film for separating the diffusion layers. Hereinafter, such phenomenon is referred to as "a rising-up". Alternately, the electrical short-circuits originate from the formation of the conductive material. In order to prevent the rising-up of the titanium silicide and the formation of the conductive material, lengthening of an etching time to etch the non-reactive titanium silicide causes the titanium silicide on the diffusion layer to be etched excessively, leading to condition wherein the diffusion layer resistance increases.
From such viewpoint, several methods to prevent the rising-up due to the expansion of the titanium silicide into the undesired regions have been proposed.
One of them is disclosed in Japanese Patent Laid Open No. Sho 61-150216. In this method, a titanium film is formed on a silicon substrate. Thereafter, the first sinter is performed at a comparatively low temperature of 400 to 600.degree. C., whereby the titanium film is converted to a titanium silicide film by so-called siliciding reaction. A non-reactive titanium film is removed, thereby forming a high resistance titanium silicide film on diffusion layers and a gate electrode. Thereafter, the second sinter is performed at a temperature not less than 800.degree. C., thereby converting the high resistance titanium silicide film to a low resistance titanium silicide film. Because the first sinter is performed at the comparatively low temperature of 400 to 600.degree. C., this method has a feature in that the rising-up of the titanium silicide film can be prevented.
Another method is disclosed in Japanese Patent Laid Open No. Sho 59-126672. The structure of the semiconductor device manufactured by this method is shown in FIG. 4. In this method, in order to suppress the rising-up of the titanium silicide film on the side wall film and the reaction of the titanium film with the side wall film, the side wall film is formed of SiN film which is not prone to react with the titanium film.
However, the above-described methods have posed the following new problems.
The firstly described method involves the problem that with the micronizing of the diffusion layers and the gate electrode, a desired resistance can not be obtained. The reason is that because the first sinter temperature is low, the resistance of the titanium silicide is high, and the layer resistance of the diffusion layer after the second sinter is not below a desired value. In order to obtain the diffusion layer resistance below the desired value, if the second sinter temperature is increased, the problem that the titanium silicide is condensed occurs. For this reason, under the low first sinter temperature, the low resistance of the diffusion layer can not be achieved even when the rising-up of the titanium silicide can be suppressed.
In the secondly described method, though the electrical short-circuit between the gate electrode and the diffusion layer can be suppressed, it is impossible to suppress the electrical short-circuit between the diffusion layers adjacent to each other.
As described above, the electrical short-circuits between the gate electrode and the diffusion layer and between the diffusion layers adjacent to each other can not be necessarily perfectly suppressed with the conventional technologies.
In order to suppress such an electrical short-circuit perfectly, factors causing the rising-up of the titanium silicide were investigated. The rising-up of the Ti silicide is more significant in the P-type diffusion layer, so that attention was paid to P-type ion injection species. For the P-type diffusion layer to which BF.sup.2+ (mass:49) is injected as the ion injection species, the rising-up of the Ti silicide is shown in FIG. 5b. On the other hand, for the P-type diffusion layer to which B.sup.+ (mass:11) is injected as the ion injection species, no rising-up is shown in FIG. 5a. From this fact, it was proved that F in the BF.sup.2+ (mass: 49) that is the P-type ion injection species remains in the field oxide film and the side wall film, and a Ti silicide reaction inductively occurs on the field oxide film and the side wall film during performing the Ti silicide reaction, thereby creating the rising-up of the Ti silicide.
If the P-type diffusion layer is formed using B.sup.+ mass: 11) as the ion injection species, the rising-up of the Ti silicide can be suppressed. However, it is impossible to form shallow diffusion layers, so that micronizing of the semiconductor integrated circuit can not be achieved with the use of B.sup.+ (mass:11) as the ion injection species.